/**
	*****************************************************************************
	* @file     cmem7_spi.h
	*
	* @brief    CMEM7 SPI header file
	*
	*
	* @version  V1.0
	* @date     3. September 2013
	*
	* @note               
	*           
	*****************************************************************************
	* @attention
	*
	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
	* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 
	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
	*
	* <h2><center>&copy; COPYRIGHT 2013 Capital-micro </center></h2>
	*****************************************************************************
	*/
	
#ifndef __CMEM7_SPI_H
#define __CMEM7_SPI_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "cmem7.h"
#include "cmem7_conf.h"

#define SPI_MODE_CPOL_0_CPHA_0         0   /*!< CPOL : idle clock level. CPHA : capture data at 1st or 2nd edge */
#define SPI_MODE_CPOL_0_CPHA_1         1
#define SPI_MODE_CPOL_1_CPHA_0         2
#define SPI_MODE_CPOL_1_CPHA_1         3	     

#define IS_SPI_MODE(MODE)              (((MODE) == SPI_MODE_CPOL_0_CPHA_0) || \
                                        ((MODE) == SPI_MODE_CPOL_0_CPHA_1) || \
                                        ((MODE) == SPI_MODE_CPOL_1_CPHA_0) || \
																				((MODE) == SPI_MODE_CPOL_1_CPHA_1))
	
#define SPI_INT_RX_FIFO_UNDERFLOW      0x00000001    
#define SPI_INT_RX_FIFO_OVERFLOW       0x00000002
#define SPI_INT_RX_FIFO_ALMOST_FULL    0x00000004
#define SPI_INT_TX_FIFO_UNDERFLOW      0x00000008    
#define SPI_INT_TX_FIFO_OVERFLOW       0x00000010
#define SPI_INT_TX_FIFO_ALMOST_FULL    0x00000020
#define SPI_INT_DONE                   0x00000040
#define SPI_INT_ALL                    0x0000007F

#define IS_SPI_INT(INT)                (((INT) & ~SPI_INT_ALL) == 0)


typedef struct
{
  uint8_t SPI_Mode;                 /*!< indicates SPI's CPOL and CPHA */
  BOOL SPI_RxEn;                    /*!< indicates if SPI receiver is enabled or not */
  uint8_t SPI_BitLength;            /*!< bit length while transmitting and receiving */
  uint8_t SPI_Gap;                  /*!< cycle number between continuous data frame */ 
} SPI_InitTypeDef;



#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI0) || \
                                   ((PERIPH) == SPI1))


void SPI_Init(SPI0_Type* SPIx, SPI_InitTypeDef *init);
void SPI_Enable(SPI0_Type* SPIx, BOOL enable);
void SPI_EnableInt(SPI0_Type* SPIx, uint32_t Int, BOOL enable);
BOOL SPI_GetIntStatus(SPI0_Type* SPIx, uint32_t Int);
void SPI_ClearInt(SPI0_Type* SPIx, uint32_t Int);
/* return value is actual read data size */
uint8_t SPI_Read(SPI0_Type* SPIx, uint8_t size, uint32_t* data);
/* return value is actual write data size */
uint8_t SPI_Write(SPI0_Type* SPIx, uint8_t Size, uint32_t* data);
BOOL SPI_Transcation(SPI0_Type* SPIx, uint8_t size);

#ifdef __cplusplus
}
#endif

#endif /*__CMEM7_SPI_H */

